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T6N71B 2002-02-13 1 toshiba cmos digital integrated circuit silicon monolithic T6N71B rfid (radio frequency tag) reader and writer interface lsi features rfid reader and writer interface lsi embedding analog and data processing receive signal demodulation circuit stabilized by a built-in digital pll. the antenna, capacitors, band pass filter, and other features are external, therefore selectable. built-in modulation circuit for transmit carrier supports rfid lsi (toshiba general-purpose t6n38/46/78). conforms to iso14443 (type b) and iso13506. supplied as bare chip or lqfp48 clock sync serial interface/start-stop sync serial interface for interfacing with cpu sync circuit (crossed line protection) in case of multiple readers in simultaneous operation transmit/receive control by register built-in oscillator circuit power supply voltage detection circuit for battery use weight: 384 mg (typ.)
T6N71B 2002-02-13 2 1. product outline 1.1 product name: T6N71B 1.2 structure: cmos monolithic ic 1.3 use: reader interface lsi for rfid reader/writer 1.4 function: analog circuit: receive amplifier, voltage detection circuit, and oscillator circuit logic circuit: transmit circuit, modulation circuit, demodulation circuit, digital pll circuit, cpu interface, pc interface 2. absolute maximum ratings parameter symbol operating rating unit operating ambient temperature t opr 20~80 c storage temperature t stg 40~125 c power supply voltage v dd 0.3~6.0 v input voltage v in gnd 0.3~v dd 0.3 v power dissipation p d 150 mw or less (based on heat allowance for plastic package)
T6N71B 2002-02-13 3 3. system configuration 3.1 diagram of system configuration 3.2 example of overall system configuration lcd, led, etc. port1 port2 /sck (sio port) so (sio port) si (sio port) cpu rfid /rst cont /sck si so T6N71B lsi for rf card reader i/f (lqfp48) modulation circuit amp0 cpu interface, pc interface, frequency divider control register amp1 comp oscillator circuit voltage detection circuit demodulation circuit logic circuit receive circuit v dd _ t x psk_txd0 psk_txd1 gnd_t x mod_out v dd _a amp0_in0 bypass gnd_ a amp0_in1 amp0_out cont pll_lock si so v dd _d psk_rxd sync_in sync_out gnd_d osc_out /sck gnd_d /rst sio_err v dd _d syn_asyn gnd_d pc_txd pc_rxd pc_sck baud_sel0 baud_sel1 amp1_in0 amp1_in1 gnd_osc xout xin vdd_osc /bup /xe vdet1 vdet0 /vdeten
T6N71B 2002-02-13 4 3.3 example of application system configuration 1 (toshiba general-purpose rfid lsi, t6n38/46/78) 3.4 example of application system configuration 2 (iso14443 type b rfid) transmission antenna circuit transmission driver receive antenna circuit bpf bpf modulation circuit amp0 cpu interface, pc interface, frequency divider control register amp1 comp oscillator circuit voltage detection circuit demodulation circuit logic circuit receive circuit transmission/ receive antenna circuit bpf bpf modulation circuit amp0 cpu interface, pc interface, frequency divider control register amp1 comp oscillator circuit voltage detection circuit demodulation circuit logic circuit receive circuit ask modulation circuit detection wave circuit amp
T6N71B 2002-02-13 5 4. electrical characteristics 4.1.1 operating characteristics (ta 20c~80c) (5 v operation) item test condition min typ. max unit remarks operating voltage v dd gnd 0 v 4.5 5.0 5.5 v operating frequency 2 20 mhz operating current 1 (trans) v dd 5.5 v, 8 mhz 8 14 ma * 1 operating current 2 (receive 1) v dd 5.5 v, 8 mhz 9 15 ma * 1 operating current 3 (receive 2) v dd 5.5 v, 8 mhz 10 16 ma * 1 bld operating current v dd 5.5 v 120 250 a * 1 halt current v dd 5.5 v 3 20 a * 1 * 1: both operating and halt currents are consumed only by the lsi. that is, apart from the input pins and oscillation circuit, all related output pins are open and have no load. operating current 1: current consumption at internal logic operation and 125 khz carrier output operating current 2: current consumption at internal logic operation, 125 khz carrier output, and amplifier (amp0 only) in operation operating current 3: current consumption at internal logic operation, 125 khz carrier output, and amplifiers (both amp0 and amp1) in operation bld operating current: current consumption when only voltage detection circuit in operation halt current: dissipation current in halt mode (wait state) 4.1.2 operating characteristics (ta 20c~80c) (3 v operation) item test condition min typ. max unit remarks operating voltage v dd gnd 0 v 2.5 3.0 3.3 v operating frequency 2 14 mhz operating current 1 (trans) v dd 3.3 v, 8 mhz 5 9 ma * 1 operating current 2 (receive 1) v dd 3.3 v, 8 mhz 6 10 ma * 1 operating current 3 (receive 2) v dd 3.3 v, 8 mhz 7 11 ma * 1 bld operating current v dd 3.3 v 100 200 a * 1 halt current v dd 3.3 v 1 10 a * 1 * 1: both operating and halt currents are consumed only by the lsi. that is, apart from the input pins and oscillation circuit, all related output pins are open and have no load. operating current 1: current consumption at internal logic operation and 125 khz carrier output operating current 2: current consumption at internal logic operation, 125 khz carrier output, and amplifier (amp0 only) in operation operating current 3: current consumption at internal logic operation, 125 khz carrier output, and amplifiers (both amp0 and amp1) in operation bld operating current: current consumption when only voltage detection circuit in operation halt current: dissipation current in halt mode (wait state)
T6N71B 2002-02-13 6 4.2.1 dc characteristics (ta 20c~80c) (5 v operation) item symbol test condition min typ. max unit remarks l input voltage 1 vil v dd 5 v 0 v dd 0.2 v * 1 h input voltage 1 vih v dd 5 v v dd 0.75 v dd v * 1 input leakage current iih v dd 5 v, v in 5 v 1 a * 5 input leakage current iil v dd 5 v, v in 0 v 1 a * 6 l output current iol1 v dd 5 v, v out 0.5 v 1.2 ma * 2 h output current ioh1 v dd 5 v, v out 4.5 v 1.0 ma * 2 l output current iol2 v dd 5 v, v out 0.5 v 3.2 ma * 3 h output current ioh2 v dd 5 v, v out 4.5 v 2.5 ma * 3 l output current iol3 v dd 5 v, v out 0.5 v 7.0 ma * 4 h output current ioh3 v dd 5 v, v out 4.5 v 5.0 ma * 4 pull-up resistance v dd 5 v, v in 0 v 66 110 154 k * 7 * 1: applies to the following eleven input pins: /rst, psk_rxd, sync_in, si, pc_rxd, syn_asyn, baud_sel0, baud_sel1, /xe, /bup, /vdeten * 2: applies to the following seven output pins: psk_rxd, so, /sck, vdet0, vdet1, pll_lock, sio_err * 3: applies to the following five output pins: mod_out, sync_out, pc_txd, pc_sck, osc_out * 4: applies to the following two output pins: psk_txd0, psk_txd1 * 5: applies to the following eleven input pins: /rst, psk_rxd, sync_in, si, pc_rxd, syn_asyn, baud_sel0, baud_sel1, /xe, /bup, /vdeten * 6: applies to the following ten input pins: /rst, sync_in, si, pc_rxd, syn_asyn, baud_sel0, baud_sel1, /xe, /bup, /vdeten * 7: applies to the psk_rxd pin.
T6N71B 2002-02-13 7 4.2.2 dc characteristics (ta 20c~80c) (3 v operation) item symbol test condition min typ. max unit remarks l input voltage 1 vil v dd 3 v 0 v dd 0.2 v * 1 h input voltage 1 vih v dd 3 v v dd 0.75 v dd v * 1 input leakage current iih v dd 3 v, v in 3 v 1 a * 5 input leakage current iil v dd 3 v, v in 0 v 1 a * 6 l output current iol1 v dd 3 v, v out 0.5 v 1.0 ma * 2 h output current ioh1 v dd 3 v, v out 2.5 v 0.8 ma * 2 l output current iol2 v dd 3 v, v out 0.5 v 2.0 ma * 3 h output current ioh2 v dd 3 v, v out 2.5 v 1.6 ma * 3 l output current iol3 v dd 3 v, v out 0.5 v 4.0 ma * 4 h output current ioh3 v dd 3 v, v out 2.5 v 3.2 ma * 4 pull-up resistance v dd 3 v, v in 0 v 66 110 154 k * 7 * 1: applies to the following eleven input pins: /rst, psk_rxd, sync_in, si, pc_rxd, syn_asyn, baud_sel0, baud_sel1, /xe, /bup, /vdeten * 2: applies to the following seven output pins: psk_rxd, so, /sck, vdet0, vdet1, pll_lock, sio_err * 3: applies to the following five output pins: mod_out, sync_out, pc_txd, pc_sck, osc_out * 4: applies to the following two output pins: psk_txd0, psk_txd1 * 5: applies to the following eleven input pins: /rst, psk_rxd, sync_in, si, pc_rxd, syn_asyn, baud_sel0, baud_sel1, /xe, /bup, /vdeten * 6: applies to the following ten input pins: /rst, sync_in, si, pc_rxd, syn_asyn, baud_sel0, baud_sel1, /xe, /bup, /vdeten * 7: applies to the psk_rxd pin.
T6N71B 2002-02-13 8 4.2.3 internal equivalent circuits for pins input pins : /rst, psk_rxd, sync_in, si, pc_rxd, syn_asyn, baud_sel0, baud_sel1, /xe, /bup, /vdeten output pins : so, /sck, vdet0, vdet1, pll_lock, sio_err, mod_out, sync_out, pc_txd, pc_sck, osc_out, psk_txd0, psk_txd1 input/output (with pull-up resistor) pin : psk_rxd internal circuit internal circuit input/output switch signal internal circuit a t input: pull-up resistor connected, output buffer in hiz a t output: pull-up resistor disconnected, output buffer in h or l output when control register extrxd 1, the psk_rxd pin is set to output mode; when extrxd 0, set to input mode (pull-up resistor connected). v dd 110 k internal circuit
T6N71B 2002-02-13 9 4.3 oscillation characteristics (ta 20c~80c) (for your reference) item symbol test condition min typ. max unit remarks oscillation start voltage v sta crystal oscillator, 8 mhz c 10 pf, r o 0 , r f 1 m 2.2 v oscillation hold voltage v hold crystal oscillator, 8 mhz c 10 pf, r o 0 , r f 1 m 2.2 v note: evaluate and decide the external components (r f , c, r o ) in accordance with the crystal oscillator and ceramic oscillator used. before using, be sure to check the oscillation characteristics as these vary depending on the crystal or ceramic oscillator. stop (internal signal) *: connect the circuit near the xi and xo pins. *: use external r f , r o , c, and oscillator (crystal). *: when using an external clock, input from the xi pin. do not connect xi and xo pin to other external devices. * : the /bup pin is used to control the level of current to the oscillation circuit. setting /bup h reduces the dissipation current. however, this also results in a fall in the oscillation characteristics. r f xo xi to internal clock r o c c /bup
T6N71B 2002-02-13 10 4.4 power supply voltage detection circuit (ta 20c~80c) item test condition min typ. max unit remarks vdet0 2.2 2.4 2.6 v 0.2 v vdet1 3.6 4.0 4.4 v 0.4 v * : power supply voltage drop detection: when the circuit is enabled, if the v dd voltage exceeds the detected vdet0 or vdet1, high level is output; if the v dd voltage drops below the detected vdet0 or vdet1, low level is output. * : the reference voltage (v ref ) which is not dependent on the v dd voltage is internal to the lsi. the power supply voltage detection circuit inputs the voltage by extracting it from the resistance dividing block where the v dd voltage is used as the supply to the comparator. the detector compares the voltage with the reference voltage (v ref ) to detect whether the v dd voltage is below 2.4 v or 4.0 v. * : enable signal: in halt state and external pin /vdeten h input, the voltage detection circuit is disabled. enable signal v dd vdet0 comp v re f vdet1 comp v re f hazard elimination circuit delay circuit
T6N71B 2002-02-13 11 4.5.1 amplifier characteristics (ta 20c~80c) (5 v operation) item test condition min typ. max unit remarks carrier input voltage peak-to-peak 0 5.5 v * 1 amplification ratio 23 37 db amp0 amp waveform duty (sine wave input) v dd 4.5 v, v in 10 mv (rms) freq 500 khz (sine wave input) 35:65 50:50 65:35 amp1 input resistance amp_in1 v dd 0.5 v bypass v dd 36 60 84 k amp input in1 pin output impedance v in v dd 0.5 v 0.6 1 1.4 k amp0 * 1: the input voltage is the voltage which can be input to the amp0_in0, amp0_in1, amp1_in0, amp1_in1 pins. it does not specify normal operation. * 2: the above characteristic is defined by the following test circuit. amp0_in0 amp0_in1 c2 0.1 f amp0_out amp0 sg v in 10 mv (rms) bypass 50 c3 4.7 f r2 59 r1 60 k r out 1 k r1 60 k c1 0.1 f r2 330 a mp output waveform (amp0): amp0_out pin v out v dd bypass (
v dd 0.5 v) bypass 1.0 v amp1_in0 amp1_in1 c2 0.1 f rsk_rxd amp1 sg v in 10 mv (rms) bypass 50 c3 4.7 f r2 59 r1 60 k r1 60 k c1 0.1 f r2 330 comp bypass a mp output waveform (amp1): psk_rxd pin t cyc v dd gnd t half
T6N71B 2002-02-13 12 [definition] gain 20 og (v out /v in ); however, within the range where output does not saturate. duty cycle t half /t cyc 100 * : amp0 output amp0_out operates with the bypass potential ( v dd 0.5 v) as the operating point. when v in is sufficiently large, a sine wave limited to between v dd and v dd 1 v (saturated state: almost a square wave) is output. * : amp1 is connected to the binary comparator. the duty cycle is measured on the psk_rxd pin where the data are output from the comparator. (typical characteristic) 20 24 28 32 36 40 44 48 10 100 1000 10000 ta 25c v dd 5 v frequency (khz) amp gain characteristic gain (db)
T6N71B 2002-02-13 13 4.5.2 amplifier characteristics (ta 20c~80c) (3 v operation) item test condition min typ. max unit remarks carrier input voltage peak-to-peak 0 3.3 v * 1 amplification ratio 23 36 db amp0 amp waveform duty (sine wave input) v dd 3 v, v in 10 mv (rms) freq 500 khz (sine wave input) 35:65 50:50 65:35 amp1 input resistance amp_in1 v dd 0.5 v bypass v dd 36 60 84 k amp input in1 pin output impedance v in v dd 0.5 v 0.6 1 1.4 k amp0 * 1: the input voltage is the voltage which can be input to the amp0_in0, amp0_in1, amp1_in0, amp1_in1 pins. it does not specify normal operation. * 2: the above characteristics are determined by the same kind of test circuit and definitions as in 4.5.1. (typical characteristic) 20 24 28 32 36 40 44 48 10 100 1000 10000 ta 25c v dd 3 v frequency (khz) amp gain characteristic gain (db)
T6N71B 2002-02-13 14 5. pin assignment 5.1 outline of functions pin name input/ output function psk_txd0/1 output antenna output pin (carrier and data output pin) mod_out output sub carrier output pin transmit circuit v dd _tx, gnd_tx transmit-circuit-only power supply pins amp0_in0 input psk receive wave amp (amp0) input pin amp0_in1 input psk receive wave amp (amp0) input pin amp0_out output psk receive wave amp (amp0) output pin amp1_in0 input psk receive wave amp (amp1) input pin amp1_in1 input psk receive wave amp (amp1) input pin bypass amp stabilizing capacitor connecting pin receive circuit v dd _a, gnd_a receive-circuit-only power supply pins /rst input system reset input pin psk_rxd input/ output receive carrier input/output pin (pull-up resistor connected at input) sync_in input transmit sync signal input pin sync_out output transmit sync signal output pin si input cpu interface serial input (sync/start-stop sync) pin so output cpu interface serial output (sync/start-stop sync) pin /sck output serial clock (sync) /sio clock (start-stop sync) pin cont input control pin (when l, register setting mode) pc_rxd input external interface receive input (start-stop sync) pin pc_txd output external interface receive output (start-stop sync) pin pc_sck input external interface clock generation baud generator input pin syn_asyn input cpu interface clock sync/start-stop sync switching pin baud_sel0/1 input initial transfer rate select pin pll_lock output pll lock detection pin sio_err output rfid receive data (clock sync) error detection pin logic circuit v dd _d0~d01, gnd_d0~d02, v dd _osc, gnd_osc logic circuit and oscillator power supply pins xi, xo oscillation circuit. crystal oscillator, ceramic oscillator, capacitor, and external resistor are externally connected. osc_out output oscillation frequency output pin /xe input oscillator and receive circuit enable pin. when set to l, oscillation starts. /bup input oscillator beta up mode enable pin. when set to l, beta up mode. vdet0/1 output pin for detection signal output from power voltage detection circuit others /vdeten input power voltage detection circuit enable pin. when set to l, enables the detector. total: 44 pins (4 nc pins are not included.)
T6N71B 2002-02-13 15 5.2 pin assignment no. pin name no. pin name no. pin name no. pin name 1 amp1_in0 13 osc_out 25 gnd_d1 37 v dd _tx 2 amp1_in1 14 gnd_d0 26 /rst 38 psk_txd0 3 gnd_osc 15 sync_out 27 sio_err 39 psk_txd1 4 x out 16 sync_in 28 v dd _d1 40 gnd_tx 5 x in 17 psk_rxd 29 syn_asyn 41 mod_out 6 v dd _osc 18 v dd _d0 30 gnd_d2 42 v dd _a 7 /bup 19 /sck 31 pc_txd 43 amp0_in0 8 /xe 20 so 32 pc_rxd 44 bypass 9 vdet1 21 si 33 pc_sck 45 gnd_a 10 vdet0 22 pll_lock 34 baud_sel0 46 amp0_in1 11 /vdeten 23 cont 35 baud_sel1 47 amp0_out 12 n.c. 24 n.c. 36 n.c. 48 n.c. 36. n.c. 34. baud_sel0 33. pc_sck 32. pc_rxd 31. pc_txd 30. gnd_d2 29. syn_asyn 28. v dd _d1 27. sio_err 26. /rst 25. gnd_d1 37. v dd _tx 38. psk_txd0 39. psk_txd1 40. gnd_tx 41. mod_out 42. v dd _a 43. amp0_in0 44. bypass 45. gnd_a 46. amp0_in1 47. amp0_out 23. cont 22. pll_lock 21. si 20. so 19. /sck 18. v dd _d0 17. psk_rxd 16. sync_in 15. sync_out 14. gnd_d0 1. amp1_in0 2. amp1_in1 3. gnd_osc 4. x out 5. x in 6. v dd _osc 7. /bup 8. /xe 9. vdet1 10. vdet0 11. /vdeten toshiba T6N71B japan xxxx yyyyyyy 12. n.c. 13. osc_out 24. n.c. 35. baud_sel1 48. n.c.
T6N71B 2002-02-13 16 5.3 chip pad assignment and coordinates chip size: 3.2 3.2 mm pad coordinates unit: m no. pad name x coordinate y coordinate no. pad name x coordinate y coordinate no. pad name x coordinate y coordinate 1 amp1_in0 1102 1464 16 psk_rxd 1464 200 31 pc_sck 627 1464 2 amp1_in1 855 1464 17 v dd _d0 1464 0 32 baud_sel0 855 1464 3 gnd_osc 627 1464 18 /sck 1464 200 33 baud_sel1 1102 1464 4 x out 409 1464 19 so 1464 409 34 v dd _tx 1464 1102 5 x in 200 1464 20 si 1464 627 35 psk_txd0 1464 855 6 v dd _osc 0 1464 21 pll_lock 1464 855 36 psk_txd1 1464 627 7 /bup 200 1464 22 cont 1464 1102 37 gnd_tx 1464 409 8 /xe 409 1464 23 gnd_d1 1102 1464 38 mod_out 1464 200 9 vdet1 627 1464 24 /rst 855 1464 39 v dd _a 1464 0 10 vdet0 855 1464 25 sio_err 627 1464 40 amp0_in0 1464 200 11 /vdeten 1102 1464 26 v dd _d1 409 1464 41 bypass 1464 409 12 osc_out 1464 1102 27 syn_asyn 200 1464 42 gnd_a 1464 627 13 gnd_d0 1464 855 28 gnd_d2 0 1464 43 amp0_in1 1464 855 14 sync_out 1464 627 29 pc_txd 200 1464 44 amp0_out 1464 1102 15 sync_in 1464 409 30 pc_rxd 409 1464 * : pad coordinates are the pad center coordinates. * : pad opening is 100 m 100 m. 34. v dd _tx 35. psk_txd0 36. psk_txd1 37. gnd_tx 38. mod_out 39. v dd _a 40. amp0_in0 41. bypass 42. gnd_a 43. amp0_in1 44. amp0_out 22. cont 21. pll_lock 20. si 19. so 18./sck 17. v dd _d0 16. psk_rxd 15. sync_in 14. sync_out 13. gnd_d0 12. osc_out (0, 0) y direction x direction 33. baud_sel1 32. baud_sel0 31. pc_sck 30. pc_rxd 29. pc_txd 28. gnd_d2 27. syn_asyn 26. v dd _d1 25. sio_err 24. /rst 23. gnd_d1 1. amp1_in0 2. amp1_in1 3. gnd_osc 4. x out 5. x in 6. v dd _osc 7. /bup 8. /xe 9. vdet1 10. vdet0 11. /vdeten
T6N71B 2002-02-13 17 6. caution on designing peripheral circuits the lsi supports a total of eleven power supply pins (v dd and gnd) as follows: v dd _d0 to d1, gnd_d0 to d2, v dd _osc, gnd_osc, v dd _a, gnd_a, v dd _tx, and gnd_tx. because the lsi also has analog circuits, to minimize power interference between circuit blocks, the power supply is isolated among logic circuits (v dd _d0 to 1, v dd _d0 to 2, v dd _osc, and gnd_osc), analog circuits (v dd _a, gnd_a), and transmit circuits (v dd _tx, gnd_tx). thus, when designing peripheral circuits, take this into consideration and pay attention to the following points. (1) how to handle gnd pins connect the gnd pins to gnd with the same power supply on the circuit board. (2) how to handle v dd pins connect v dd _d0 to d1 and v dd _osc to the same power supply on the pcb. for the stability of the internal circuits, apply the same v dd level to the logic, analog, and transmission systems.
T6N71B 2002-02-13 18 package dimensions weight: 384 mg (typ.)
T6N71B 2002-02-13 19 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the products described in this document contain components made in the united states and subject to export control of the u.s. authorities. diversion contrary to the u.s. law is prohibited. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707ed a restrictions on product use

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